Mothra
This 22FDX silicon implements a matrix inversion accelerator for Hermitian, positive-definite matrices,
a key operation in many wireless communication algorithms such as MIMO detection and precoding.
We compute an explicit inverse of a 16×16 matrix using a block-LDL (BLDL) factorization algorithm.
Our hardware architecture is composed of a systolic array of programmable processing elements,
to i) compute the multiplication of an Hermitian matrix by its transpose (a pre-processing step prior matrix inversion for an LMMSE detector),
and to ii) compute the back-substitution step after the BLDL factorization.
The block-LDL factorization has a specialized datapath whose operations are controlled in a processor-like fashion by an FSM.
Our ASIC achieves a throughput of 1.44 M mat/s and 416 mW at 870 MHz clock frequency at a latency of 0.7 µs.
You can read our publication here.
Wormy
This 22FDX silicon implements a Low-Density Parity-Check (LDPC) decoder operating with a custom-designed short-blocklength LDPC code.
LDPC codes, together with their dedicated decoders, form a class of error-correction algorithms used to recover data corrupted by noise.
Our custom short-blocklength LDPC code outperforms the 5G standard code (of the same length) in terms of BLER/FER.
Our decoder can operate with three different rates and has an early termination engine that mutes the internal registers once a valid codeword is found,
which enables power savings. To achieve high-throughput, we inserted a second register in the critical path.
This technique, known as pipeline interleaving, allows the processing of two independent codewords simultaneously.
On this chip, we were able to feed through a 1.45 GHz clock by placing a custom-designed buffer on the die.
You can read our publication here.
